Free and Open Source Silicon Foundation
Working together for Free and Open Source Silicon
- 64
- Projects
- 11
- Years accepted
- 5
- In 2026
Projects by year
642026
5 acceptedShow
Surfer Memory and Wide Array Support
Accepted project · by Kutikuppala Deekshita
This proposal focuses on enhancing the Surfer waveform viewer by adding support for memory and wide array visualization. Current waveform views are...
Using AI to Improve Open-Source IP
Accepted project · by Muhammad Rayyan Khan
Millions of lines of open-source Verilog exist but remain verbose and hard to maintain. TL-Verilog offers a cleaner abstraction, but almost none of...
Robust Implementation and Verification of the RISC-V Svadu Extension for Ariane+OpenPiton
Accepted project · by Seongwon Jo
This project aims to bring Ariane+OpenPiton closer to RISC-V RVA23 compliance by adding support for the Svadu extension. By enabling hardware-managed...
Generate Counter Examples for Bounded Model Checks in CIRCT
Accepted project · by Shri Vishakh Devanand
circt-bmc can already prove when an assertion is falsifiable, but it does not yet produce the counterexample trace format hardware developers rely on...
Generic MinimumLinuxBoot for RTL Simulations
Accepted project · by Xuhai Chang
Booting Linux in OpenPiton's Verilator RTL simulation takes days. This project builds a checkpoint/restore pipeline: boot Linux in QEMU (minutes),...
2025
5 acceptedShow
PeakRDL Exporter Plugin for CSR Visualization on Makerchip
Accepted project · by Ali Mohsen
The project aims to add an exporter plugin for PeakRDL that enables a high level visualization for control & status register (CSR) design using...
Device-Under-Test Python Typing Stub Generator for cocotb tests
Accepted project · by chaitanyasharma
This project aims to create a tool that automatically generates Python typing stubs for the Device Under Test (DUT) in cocotb-based hardware...
Jump Label Implementation aims to eliminate branch overhead in kernel code by dynamically patching JMP/NOP instructions at runtime using GCC's...
Architectural Improvements to OpenPiton+Ariane for RISC-V Profile Compliance
Accepted project · by Jayishnu Uttane
This project aims to enhance the OpenPiton+Ariane architecture to progress toward RISC-V RVA23 profile compliance. The primary focus will be...
Modern RTL simulation is computationally expensive and often limited by single-node processing capabilities. This proposal aims to improve...
2024
6 acceptedShow
- Transforming the OpenHW High Performance Data Cache into a High Performance Instruction CacheAkiho Kawada
- Implementing RISC-V Cache Management Operation Extensions in OpenPitonSuraj Shirvankar
- Improving ATPG Fault Coverage in FaultYoussef Kandil
- TinyParrot: A minimal BlackParrot RISC-V Multicore variantColin Knizek
- Integration of Silicon Compiler Microservices into the TL-Verilog Mode in VS-CodeRaj Aryan Singh
- Arcilator VectorizationMohamed Atef
2023
5 acceptedShow
- Circuit Visualization with Makerchip PlatformChaitravi Chalke
- Enhancing OpenPiton+Ariane SoC With an Open-Source Advanced Interrupt Architecture (AIA)Kinza Qamar Zaman
- Improving SDF support in Icarus VerilogLeo Moser
- Enhancing OpenPiton+Ariane With a High-Performance Data CacheNoelia Oliete Escuín
- Parameterized device layouts for GF180MCUQurrat ul ain Alam
2022
8 acceptedShow
- Enhancing the Sootty Terminal-based Graphical Waveform ViewerYihua Liu
- IRSIM Dynamic Power Analysis and Other ImprovementsJason Liang
- Improving Query Language Features in SoottyL Lakshmanan
- Development Framework for Open MPW ShuttlesAli Imran
- Logical Equivalence Checks with CIRCTDragoș Cristian Lizan
- Enhancing AnyCore, a superscalar RISC-V processorGergely Bálint
- 1st CLaaS for PYNQ FPGAsShrihari
- TinyParrot: A minimal BlackParrot RISC-V Multicore variantKinza Qamar Zaman
2021
11 acceptedShow
- Parallelising Verilog RTL Simulations Using MPIGuillem Lopez Paradis
- M-extension support for SERVZeeshan Rafique
- Bring up CV32E40P AI accelerator on FPGAVeronia Iskandar
- Formal Verification of Mor1kx processor using Yosys-Formal toolsHarshitha S
- WARP-V Many-Core in the CloudVineet Jain
- Black Parrot on Open-Source Google-Skywater 130nm nodeLakshmi S
- Block Based Circuit DesignNinad Jangle
- Virtual FPGA LabBala Dhinesh
- Porting BaseJump STL to FuseSoCAdithya Sunil Edakkadan
- Multi-level TLB support for ArianeNazerke Turtayeva
- TensorCore Extension for Deep LearningNitin Mishra
2020
4 acceptedShow
- AUTOMATING HARDWARE AND BITSTREAM VERIFICATION FOR PRGA WITH COCOTBAnsh Puvvada
- Integrating ao486 with BYOC FrameworkManan Gupta
- Integration of WARP-V with OpenPitonShivam Potdar
- Enhancement in Warp-V and OptimizationVineetJain07
2019
7 acceptedShow
- Extend Librecores.org in terms of User Interactivity and FeedbackAquib Baig
- Microarchitectural enhancement of ArianeZach Zheng
- Analysis of WARP-V on FireSim with RocketChipAlaa Salman
- FPGA-Accelerated Web ApplicationsÁkos Hadnagy
- Enhancing JuxtaPiton with X86 SupportKunal Gulati
- Continuous Integration for Hardware Projects on LibreCores CINancy Chauhan
- LLVM Code Generation for RISC-V Open Source GPUReshabh Sharma
2018
6 acceptedShow
- Develop a Transaction-Level Verilog Component LibraryAhmed Salman
- Digital Filter Block Implementations in MyHDL and PyFDA IntegrationSriyash Caculo
- Improve the LibreCores.org in terms of discoverabilitySandip Kumar Bhuyan
- Formal verification of WARP-V processorÁkos Hadnagy
- BaseJump STL Hackerkunalgulati
- Enable DEVSIM to simulate solar cellsNoe Nieto
2017
4 acceptedShow
- Integration of OpenRISC Linux Port into OpTiMSoCPedro Henrique Penna
- EDSAC Museum on FPGAhatim
- Quality metrics for projects listed on LibreCores.orgAmitosh Swain Mahapatra
- Updating Sodorkritik bhimani
2016
3 acceptedShow
- QEMU port of OpenRISCDalmon Ian
- Yosys Tools: Automatic schematic generation for web browsersRishabh Rawat
- RISC-V port to Parallelaeliaskousk
